In semiconductor memory circuits a memory cell, when accessed, drives a column line, which may also be termed a bit line, to a high or low state as a function of the data stored in the memory cell. It has been the typical practice to transmit the data state on the bit line through an enhancement type transistor to an input/output line. As integrated circuits have been developed to utilize relatively low (5.0 volt) supply voltages the amplitude of driving voltages for transistors has become critical. With reduced fabrication geometries and lower voltages it has become increasingly difficult to detect the small data signals produced by memory cells. To transfer a data state from a bit line to an I/O line there must be a minimum of resistance through the data transfer transistor which is also referred to as a column select transistor. It is well known that the conductivity of an FET transistor is proportional to its size and to the applied gate-to-source voltage. As available voltages have become less there has been a proportionate need to increase the size of the data transfer transistor. But since there is one data transfer transistor for each one or group of memory cells the resulting increase in size can be significant for the overall circuit.
In view of the above problems regarding driving voltage and size for data transfer transistors there exists a need for a memory cell circuit in which there is a substantially greater drive voltage applied to the data transfer transistors such that the transistor can be fabricated to have a lesser size.